Friday, May 27, 2005
The Consumer IC Market:: Dwidgetal Devices
Posting before the weekend.....
Before my presentation to SEMI Austin this past Tuesday I was browsing the gadget sites.
This wandering included: Engadget, Gizmodo, Slash.org, Russell Beattie's Notebook and Mobitopia.
I am getting RSS feeds for all of these via Bloglines. Yeah, I know, too much time spent at these sites results in information overload. With so many sites out there you have to wonder how many people suffer from internet-induced attention deficit disorder (ADD).
But back to the point. The primary purpose of these gadget sites is to preview, review and discuss, the latest and greatest electronic gadgetry. In the near term this is a noble and overwhelming cause. Whether the sites survive over the long run remains to be seen. For now, they are in the game.
The sites are not the issue though. What I find most interesting is the seemingly endless stream of product flow they have to digest. For our purposes, this product flow should be noted as the primary driver of growth in the Consumer IC market. This category is making a profound influence on the business model of the chip manufacturing community. I sense that the answer to "who will survive and thrive in the electronics food chain?" can be found in this arena. One of my fears is that the answer is charging at us like a mad bull and it will blindside us before we have time to react.
Calling it the Consumer IC market is boring. I've decided that from now on I am going to call these items "Dwidgetal Devices" because, these products are, for all intensive purposes, digital widgets.
There's a story here and I have not quite got my arms around it. The Widget Maker - the classic B-School case study. Hmmm..... Comments?
Saturday, May 07, 2005
The Right Questions
The Right Questions
"Equipment Life Cycle Management" will be addressed in a panel discussion at the Strategic Business Conference this week. This is a subject that is near and dear to my heart. The content is quite relevant to the post I made Thursday (the post is below this message - it's called "Capacity Observations").
Fortunes have been made procuring and selling the excess equipment produced during the bubble years. It's not just the excess production that generated this wealth, equipment from fabs that were shutdown was also purchased by distributors and channeled to many different companies in the chip manufacturing industry. Most in the industry know that China's device makers have absorbed a lot of these tools. One could even go as far to say this market is really the driver of the semiconductor manufacturing ramp in China.
The quantity and even the capability of the tools moved through these channels should not be under-estimated. Complete fabs have been auctioned and then resold. As one example, Motorola shut down more than 20 facilities, both back and front end, during their reorganization. There are many, many others that have done the same. OEM capital equipment companies have also been moving tools into the market. Some of these are older tools but a great percentage are tools that were used in development labs. For many device manufacturers development lab tools are a great deal because their capabilities often exceed the process requirements used in their fabs.
Personally, I think device production from this "recycled" capacity is greatly under-estimated by many that follow the industry. I also believe that this business is something that has a great influence on semiconductor capital equipment spending ratios. Why? Because the equipment sales numbers used to calculate capital spending ratios is based on sales reported by global OEM tool manufacturers. The numbers do not include sales made by entities that buy and resell equipment purchased at fab auctions. The numbers also do not include the tools that refurbishment houses send back in to the market.
Recent announcements from OEM capital equipment companies make it pretty clear that this older, but still production worthy market, is something that must be acknowledged. That interest is what prompted the SBC Committee to put the "Equipment Life Cycle Management" panel discussion on the agenda.
Here's a backgrounder on the discussion that will take place at SBC:
Today, approximately 40% of global device production capacity is on 6 inch or smaller wafers and >20 year old device technology (>0.5u). And, 64% of all fabs globally are >8 years old, with global average fab life of 12.8 years. These facts present some difficult challenges to the Semiconductor device manufacturers and the OEMs that supply the equipment for the fabs. Did we really expect that these conditions would prevail 20 years ago when those earlier technologies and equipment designs were first installed? Were the Semiconductor manufacturers' asset depreciation models based upon fab and equipment lifetimes of 15 to 25 years? Were the OEMs' support strategies designed with this extended life-cyle in mind? What is the true market life of a device technology? What is the true useful life of semiconductor capital equipment? Clearly, in the case of the newer leading edge fabs the focus is on CapEx and ROI. In the case of the more mature fabs, the focus moves to OpEx. Faced with these realities, what are the strategies that the device manufacturers and the OEMs should pursue to insure the greatest return for their customers and their shareholders?
Great questions.... Let's toss in one more, contributed by one of the panel participants representing a device manufacturer:
What other suppliers come into play with mature equipment in addition to the equipment OEM and the original leading edge device manufacturer? These could include other device manufacturers with different product portfolios, third party parts and service suppliers, licensed (or unlicensed) third party equipment suppliers, etc. There is a whole different value chain here other than the original one.
Lots of things to consider here.
I know, I use this quote from Bob Dylan a lot but it seems very appropriate, "The times, they are a changin'"
In the publications I send to readers (subscribers) and the various blogs at this site I am going to write a lot more about this. It's a huge issue.
Silicon Shipments: SEMI Q1 Data Another item related to my "Capacity Observations" post last Thursday hit the wires late in the week: SAN JOSE, Calif., May 5, 2005 – Worldwide silicon wafer area shipments decreased less than 2 percent during the first quarter 2005 when compared to the fourth quarter 2004 areas shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. Total silicon wafer area shipments were 1,465 million square inches during the most recent quarter, down from the 1,486 million square inches shipped during the previous quarter. The new quarterly total area shipments are 4 percent below first quarter 2004 shipments. "Coming off of a record year, we expected and experienced a slight drop in unit shipments during the first quarter of 2005" said Makoto Tsukada, chairman SEMI SMG and general manager of Shin-Etsu Handotai Co., Ltd. "However, we continue to see strong sequential growth in 300 mm wafer shipments."
Quarterly Silicon Area Shipment Trends Silicon Shipments- Millions of Square Inches
Comments and questions are welcome.
Silicon Shipments: SEMI Q1 Data Another item related to my "Capacity Observations" post last Thursday hit the wires late in the week: SAN JOSE, Calif., May 5, 2005 – Worldwide silicon wafer area shipments decreased less than 2 percent during the first quarter 2005 when compared to the fourth quarter 2004 areas shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. Total silicon wafer area shipments were 1,465 million square inches during the most recent quarter, down from the 1,486 million square inches shipped during the previous quarter. The new quarterly total area shipments are 4 percent below first quarter 2004 shipments. "Coming off of a record year, we expected and experienced a slight drop in unit shipments during the first quarter of 2005" said Makoto Tsukada, chairman SEMI SMG and general manager of Shin-Etsu Handotai Co., Ltd. "However, we continue to see strong sequential growth in 300 mm wafer shipments."
Quarterly Silicon Area Shipment Trends Silicon Shipments- Millions of Square Inches
| Q1 2004 | Q4 2004 | Q1 2005 | |
| Polished | 1,130 | 1,114 | 1,107 |
| Epitaxial | 336 | 314 | 307 |
| Nonpolished | 63 | 58 | 51 |
| TOTAL | 1,529 | 1,486 | 1,465 |
Comments and questions are welcome.
Thursday, May 05, 2005
Capacity Observations....
Just returned from a trip to Grenoble, France to present an industry outlook at the Brewer Science Lithography Symposium. Beautiful place. Great meeting. To say that I learned a bit during my trip is an understatement. The notes I took will go in the issue of the newsletter I am working on right now.
Next week is SEMI's Strategic Business Conference. That should be a great session with a number of first-rate presentations and two very timely panel discussions. Details about this event can be found at SEMI's website: http://www.semi.org and in a post a bit further down this page.
I'll be taking a lot of notes about this session and they will be complied for the reading enjoyment of fully paid-up subscribers: http://www.infras.com/monsub.html
Capacity Observations.... Here's a set of observations that I think we should give some consideration as we look at the current rate of capital spending and semiconductor industry capacity: One of the big concerns that I have mentioned about the capacity front is the potential for incremental yield improvements taking hold in the manufacture of devices at 130nm and 90nm nodes. These observations are focused on the leading edge, where the majority of capital spending takes place, but similar yield improvements are happening across the larger nodes - particularly in China. An improvement in yields, say from 40% to 60%, means a 50% increase in final die output. Okay, simple enough.... This is taking time to happen because process, design challenges, and the move to 300mm are making this particular migration along Moore's Law a much more incremental transition. Capacity brought about by increased yields should not be under-estimated. I could lean to more optimistic on the yield front for these technologies and bump current manufacturing yields to 50%. A 5% improvement in yields from that level, 50% to 55%, generates a 10% increase in final die output. This may not seem like a lot but the compound average growth rate of industry unit volumes is right around 10% per year. In talking with people in the industry influence of improving yields is quite a concern and too often overlooked. It's also a concern for investors although and I think it is a reason why the semiconductor capital equipment spending ratio is not as higher percentage of total semiconductor revenues as it has been in the past when we are setting highs in chip sales. Today semiconductor sales are tracking around all time high levels. There are a wide range of projections this year. Many think chip sales will be flat, slightly up, or slightly down (the U, V, W, or Canoe thing....) Let's forget forecasting for the moment. My point is, unit and revenue generation by chip companies is hovering around last year's run rate even though we are not seeing a big increase in the capital spending ratios. Fab utilization rates, as popularly measured by the SIA and others, have been going down (one forecasting body is saying they have flat-lined recently). Based on what we've heard in this quarter's earnings reports utilization rates are probably heading lower. Now that is interesting. How can utilization rates go down when chip sales are near record highs? I think as we go forward it will be important to factor yield improvement into the equation. I mentioned that a 50% increase in die output is possible if we see a 20% jump in final yields. This is quite plausible and it allows you to paint a very interesting scenario: Companies can actually cut wafer starts as yields go up and still see increases in final device production. There are other things lurking in the shadows that will probably exacerbate the capacity situation. A few weeks ago Merrill Lynch published a study showing the last two years of foundry capacity additions. The top 4 foundries increased capacity about 25% in '04 and 30% in '05. Would it have been necessary to put this amount capacity in place if yields on their 130nm and 90nm processes were higher? Hmmm...... Seems to me they are compensating for lower yields - although some of this could be attributed to the transition to newer wafer processing technologies. But if yields go up.... Uh oh! Yes, time will tell. One more thing to add to the mix is the efficiency of today's process tool vs. the tools of the past. Tools are much, much better - and this is aside from the fact that they are processing larger wafers. I've heard from one OEM that some of their tools are 50% faster than they were 4 years ago. Then there is the automation aspect... Wafers are being moved more efficiently (at least that is what the automation companies will tell you). What am I saying here? I believe these factors will ultimately translate into lower equipment sales - and that is what we see in the capital spending ratios. The industry is getting more bang for the spending buck. Oh, I don't doubt that we'll see another equipment order "dogpile" because it is inherent in the psyche of the chipmaker to chase market share and Moore's Law - despite the capacity situation, the economics of the market, and the financial consequences. Certainly the possibility of one more round, perhaps a muted one, of equipment purchasing for the sub-90nm regime is plausible. Generally though I see the end market for semiconductor capital equipment narrowing further because of the technological and financial challenges of moving to 65nm and 45nm. The pace of migrations along Moore's Law, with exception taken for the aggressive pursuit of it by Intel, appears to be slowing. I realize that some of this might not be clear or, even seem like a stretch to many, so I'll try and polish the viewpoint a bit more over the coming days. Feedback and questions are welcome.
Capacity Observations.... Here's a set of observations that I think we should give some consideration as we look at the current rate of capital spending and semiconductor industry capacity: One of the big concerns that I have mentioned about the capacity front is the potential for incremental yield improvements taking hold in the manufacture of devices at 130nm and 90nm nodes. These observations are focused on the leading edge, where the majority of capital spending takes place, but similar yield improvements are happening across the larger nodes - particularly in China. An improvement in yields, say from 40% to 60%, means a 50% increase in final die output. Okay, simple enough.... This is taking time to happen because process, design challenges, and the move to 300mm are making this particular migration along Moore's Law a much more incremental transition. Capacity brought about by increased yields should not be under-estimated. I could lean to more optimistic on the yield front for these technologies and bump current manufacturing yields to 50%. A 5% improvement in yields from that level, 50% to 55%, generates a 10% increase in final die output. This may not seem like a lot but the compound average growth rate of industry unit volumes is right around 10% per year. In talking with people in the industry influence of improving yields is quite a concern and too often overlooked. It's also a concern for investors although and I think it is a reason why the semiconductor capital equipment spending ratio is not as higher percentage of total semiconductor revenues as it has been in the past when we are setting highs in chip sales. Today semiconductor sales are tracking around all time high levels. There are a wide range of projections this year. Many think chip sales will be flat, slightly up, or slightly down (the U, V, W, or Canoe thing....) Let's forget forecasting for the moment. My point is, unit and revenue generation by chip companies is hovering around last year's run rate even though we are not seeing a big increase in the capital spending ratios. Fab utilization rates, as popularly measured by the SIA and others, have been going down (one forecasting body is saying they have flat-lined recently). Based on what we've heard in this quarter's earnings reports utilization rates are probably heading lower. Now that is interesting. How can utilization rates go down when chip sales are near record highs? I think as we go forward it will be important to factor yield improvement into the equation. I mentioned that a 50% increase in die output is possible if we see a 20% jump in final yields. This is quite plausible and it allows you to paint a very interesting scenario: Companies can actually cut wafer starts as yields go up and still see increases in final device production. There are other things lurking in the shadows that will probably exacerbate the capacity situation. A few weeks ago Merrill Lynch published a study showing the last two years of foundry capacity additions. The top 4 foundries increased capacity about 25% in '04 and 30% in '05. Would it have been necessary to put this amount capacity in place if yields on their 130nm and 90nm processes were higher? Hmmm...... Seems to me they are compensating for lower yields - although some of this could be attributed to the transition to newer wafer processing technologies. But if yields go up.... Uh oh! Yes, time will tell. One more thing to add to the mix is the efficiency of today's process tool vs. the tools of the past. Tools are much, much better - and this is aside from the fact that they are processing larger wafers. I've heard from one OEM that some of their tools are 50% faster than they were 4 years ago. Then there is the automation aspect... Wafers are being moved more efficiently (at least that is what the automation companies will tell you). What am I saying here? I believe these factors will ultimately translate into lower equipment sales - and that is what we see in the capital spending ratios. The industry is getting more bang for the spending buck. Oh, I don't doubt that we'll see another equipment order "dogpile" because it is inherent in the psyche of the chipmaker to chase market share and Moore's Law - despite the capacity situation, the economics of the market, and the financial consequences. Certainly the possibility of one more round, perhaps a muted one, of equipment purchasing for the sub-90nm regime is plausible. Generally though I see the end market for semiconductor capital equipment narrowing further because of the technological and financial challenges of moving to 65nm and 45nm. The pace of migrations along Moore's Law, with exception taken for the aggressive pursuit of it by Intel, appears to be slowing. I realize that some of this might not be clear or, even seem like a stretch to many, so I'll try and polish the viewpoint a bit more over the coming days. Feedback and questions are welcome.
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