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Semiconductor Manufacturing Tour
Table of Contents
The Chip-Making Process
Making the Wafer
The Mask-Making Process
Epitaxy
Photolithography Process
Oxidation & Exposure
Etch & Strip
Diffusion & Implant
Deposition
Oxidation
Interconnect - Vias
Interconnect - Metallization
Chemical Mechanical Planarization
Interconnect - Layers
Inspection & Measurement
Yield Impact.......
Test, Assembly & Packaging
Wafer Probe or Test
Memory Repair
Assembly & Packaging
Package Test
The Chip-Making Process
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Slide 11 of 22
Notes:
Again using reticles and photolithography, contact areas in the silicon dioxide are unmasked so that they can be etched all the way down to the silicon and polysilicon areas of the transistor's source, drain and gate regions.
These holes, called "vias" are essentially chemically "drilled" holes which expose the contacts to the three-terminals of the transistor.
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