Thursday, May 05, 2005

Capacity Observations....

Just returned from a trip to Grenoble, France to present an industry outlook at the Brewer Science Lithography Symposium. Beautiful place. Great meeting. To say that I learned a bit during my trip is an understatement. The notes I took will go in the issue of the newsletter I am working on right now. Next week is SEMI's Strategic Business Conference. That should be a great session with a number of first-rate presentations and two very timely panel discussions. Details about this event can be found at SEMI's website: http://www.semi.org and in a post a bit further down this page. I'll be taking a lot of notes about this session and they will be complied for the reading enjoyment of fully paid-up subscribers: http://www.infras.com/monsub.html
Capacity Observations.... Here's a set of observations that I think we should give some consideration as we look at the current rate of capital spending and semiconductor industry capacity: One of the big concerns that I have mentioned about the capacity front is the potential for incremental yield improvements taking hold in the manufacture of devices at 130nm and 90nm nodes. These observations are focused on the leading edge, where the majority of capital spending takes place, but similar yield improvements are happening across the larger nodes - particularly in China. An improvement in yields, say from 40% to 60%, means a 50% increase in final die output. Okay, simple enough.... This is taking time to happen because process, design challenges, and the move to 300mm are making this particular migration along Moore's Law a much more incremental transition. Capacity brought about by increased yields should not be under-estimated. I could lean to more optimistic on the yield front for these technologies and bump current manufacturing yields to 50%. A 5% improvement in yields from that level, 50% to 55%, generates a 10% increase in final die output. This may not seem like a lot but the compound average growth rate of industry unit volumes is right around 10% per year. In talking with people in the industry influence of improving yields is quite a concern and too often overlooked. It's also a concern for investors although and I think it is a reason why the semiconductor capital equipment spending ratio is not as higher percentage of total semiconductor revenues as it has been in the past when we are setting highs in chip sales. Today semiconductor sales are tracking around all time high levels. There are a wide range of projections this year. Many think chip sales will be flat, slightly up, or slightly down (the U, V, W, or Canoe thing....) Let's forget forecasting for the moment. My point is, unit and revenue generation by chip companies is hovering around last year's run rate even though we are not seeing a big increase in the capital spending ratios. Fab utilization rates, as popularly measured by the SIA and others, have been going down (one forecasting body is saying they have flat-lined recently). Based on what we've heard in this quarter's earnings reports utilization rates are probably heading lower. Now that is interesting. How can utilization rates go down when chip sales are near record highs? I think as we go forward it will be important to factor yield improvement into the equation. I mentioned that a 50% increase in die output is possible if we see a 20% jump in final yields. This is quite plausible and it allows you to paint a very interesting scenario: Companies can actually cut wafer starts as yields go up and still see increases in final device production. There are other things lurking in the shadows that will probably exacerbate the capacity situation. A few weeks ago Merrill Lynch published a study showing the last two years of foundry capacity additions. The top 4 foundries increased capacity about 25% in '04 and 30% in '05. Would it have been necessary to put this amount capacity in place if yields on their 130nm and 90nm processes were higher? Hmmm...... Seems to me they are compensating for lower yields - although some of this could be attributed to the transition to newer wafer processing technologies. But if yields go up.... Uh oh! Yes, time will tell. One more thing to add to the mix is the efficiency of today's process tool vs. the tools of the past. Tools are much, much better - and this is aside from the fact that they are processing larger wafers. I've heard from one OEM that some of their tools are 50% faster than they were 4 years ago. Then there is the automation aspect... Wafers are being moved more efficiently (at least that is what the automation companies will tell you). What am I saying here? I believe these factors will ultimately translate into lower equipment sales - and that is what we see in the capital spending ratios. The industry is getting more bang for the spending buck. Oh, I don't doubt that we'll see another equipment order "dogpile" because it is inherent in the psyche of the chipmaker to chase market share and Moore's Law - despite the capacity situation, the economics of the market, and the financial consequences. Certainly the possibility of one more round, perhaps a muted one, of equipment purchasing for the sub-90nm regime is plausible. Generally though I see the end market for semiconductor capital equipment narrowing further because of the technological and financial challenges of moving to 65nm and 45nm. The pace of migrations along Moore's Law, with exception taken for the aggressive pursuit of it by Intel, appears to be slowing. I realize that some of this might not be clear or, even seem like a stretch to many, so I'll try and polish the viewpoint a bit more over the coming days. Feedback and questions are welcome.

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